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freescale semiconductor data sheet: technical data document number: mcf52259 rev. 3, 5/2010 ? freescale semiconductor, inc., 2010. all rights reserved. freescale reserves the right to change the deta il specifications as may be required to permit improvements in the design of its products. mcf52259 lqfp?144 20 mm x 20 mm mapbga?144 13 mm x 13 mm lqfp?100 14 mm x 14 mm the mcf52259 microcontroller family (mcf52252, mcf52254, mcf52255, mcf52256, mcf52258, and mcf52259 devices) is a member of the coldfire ? family of reduced instruction set computing (risc) microprocessors. this document provides an overview of the 32-bit mcf52259 microcontroller, focusing on its highly integrated and diverse feature set. this 32-bit device is based on the version 2 coldfire core operating at a frequency up to 80 mhz, offering high performance and low power consumption. on-chip memories connected tightly to the pro cessor core include up to 512 kbytes of flash memory and 64 kbytes of static random access memory (sram). on-chip modules include: ? v2 coldfire core delivering 76 mips (dhrystone 2.1) at 80 mhz running from internal flash memory with enhanced multiply accumulate (mac) unit and hardware divider ? cryptography accel eration unit (cau) ? fast ethernet controller (fec) ? mini-flexbus external bus interface available on 144 pin packages ? universal serial bus on-the-go (usbotg) ? usb transceiver ? flexcan controller area network (can) module ? three universal asynchronous/synchronous receiver/transmitters (uarts) ? two inter-integrated circuit (i2c?) bus interface modules ? queued serial peripheral interface (qspi) module ? eight-channel 12-bit fast analog-to-digital converter (adc) with simultaneous sampling ? four-channel direct memo ry access (dma) controller ? four 32-bit input capture/output compare timers with dma support (dtim) ? four-channel general-purpose timer (gpt) capable of input capture/output compare, pulse width modulation (pwm), pulse-code modula tion (pcm), and pulse accumulation ? eight-channel/four-channel, 8-bit/16-bit pulse width modulation timer ? two 16-bit periodic interrupt timers (pits) ? real-time clock (rtc) module with 32 khz crystal ? programmable software watchdog timer ? secondary watchdog timer with independent clock ? interrupt controller capable of handling 57 sources ? clock module with 8 mhz on-chip relaxation oscillator and integrated phase-locked loop (pll) ? test access/debug port (jtag, bdm) mcf52259 coldfire microcontroller because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 2 table of contents 1 family configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 2.2 current consumption . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 flash memory characteristics . . . . . . . . . . . . . . . . . . .28 2.5 ezport electrical specifications . . . . . . . . . . . . . . . . . .29 2.6 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.7 dc electrical specifications . . . . . . . . . . . . . . . . . . . . .30 2.8 clock source electrical specifications . . . . . . . . . . . . .31 2.9 usb operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.10 mini-flexbus external interface specifications . . . . . . .32 2.11 fast ethernet timing specifications . . . . . . . . . . . . . . 33 2.12 general purpose i/o timing . . . . . . . . . . . . . . . . . . . . 35 2.13 reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.14 i 2 c input/output timing specifications . . . . . . . . . . . . 37 2.15 analog-to-digital converter (adc) parameters. . . . . . 38 2.16 equivalent circuit for adc inputs . . . . . . . . . . . . . . . . 39 2.17 dma timers timing specifications . . . . . . . . . . . . . . . 40 2.18 qspi electrical specifications . . . . . . . . . . . . . . . . . . . 40 2.19 jtag and boundary scan timing . . . . . . . . . . . . . . . . 40 2.20 debug ac timing specifications . . . . . . . . . . . . . . . . . 43 3 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 4 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 3 1 family configurations table 1. mcf52259 family configurations module 52252 52254 52255 52256 52258 52259 version 2 coldfire core with emac (enhanced multiply-accumulate unit) and cau (cryptographic acceleration unit) ?????? system clock up to 66 or 80 mhz 1 1 66 mhz = 63 mips; 80 mhz = 76 mips up to 80 mhz 1 up to 66 or 80 mhz 1 up to 80 mhz 1 performance (dhrystone 2.1 mips) up to 63 or 76 flash 256 kb 512 kb 512 kb 256 kb 512 kb 512 kb static ram (sram) 32 kb 64 kb 64 kb 32 / 64 kb 64 kb 64 kb two interrupt controllers (intc) ?????? fast analog-to-digital converter (adc) ?????? usb on-the-go (usb otg) ?????? mini-flexbus external bus interface ? ? ? ??? fast ethernet controller (fec) ?????? random number generator and cryptographic acceleration unit (cau) ?? ? ?? ? flexcan 2.0b module varies varies ? varies varies ? four-channel direct-memory access (dma) ?????? software watchdog timer (wdt) ?????? secondary watchdog timer ?????? t w o - c h a n n e l p e ri o d i c i n t e r ru p t t i m e r ( p i t )222222 four-channel general purpose timer (gpt) ?????? 3 2 - b i t d m a t i m e r s 444444 qspi ?????? u a r t ( s ) 333333 i 2 c 222222 eight/four-channel 8/16-bit pwm timer ?????? general purpose i/o module (gpio) ?????? chip configuration and reset controller module ?????? background debug mode (bdm) ?????? jtag - ieee 1149.1 test access port ?????? package 100 lqfp 144 lqfp or 144 mapbga because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 4 1.1 block diagram figure 1 shows a top-level block diagram of the device. package opti ons for this family are described later in this document. figure 1. block diagram 1.2 features 1.2.1 feature overview the mcf52259 family includes the following features: ? version 2 coldfire variable -length risc processor core ? static operation ? 32-bit address and data paths on-chip mini-flexbus arbiter interrupt controllers qspi uarts 0?2 i 2 c dtims 0?3 v2 coldfire cpu ifp oep emac 4 ch dma mux jtag ta p up to 64 kbytes sram (4k 16) 4 up to 512kbytes flash (64k 16) 4 ports (gpio) ccm, rstin rstout i2cs uarts dtin n /dtout n canrx jtag_en adc an[7:0] v rh v rl pll clkgen extal xtal clkout gpt pwm cantx pmm padi ? pin muxing ezport ezpcs pwm n usb fec ezpq ezpd ezpck rtc cau to / fr o m reset mini-flexbus pa d i usb pits 0?1 flexcan edge port 0?1 rnga watchdog timer gpt n qspi irq n fec ezport to/from padi to/from padi to / fr o m pa d i jtag/bdm because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 5 ? up to 80 mhz processor core frequency ? 40 mhz or 33 mhz peripheral bus frequency ? sixteen general-purpose, 32-bit data and address registers ? implements coldfire isa_a with extensions to support th e user stack pointer register and four new instructions for improved bit processing (isa_a+) ? enhanced multiply-accumulate (emac) unit with four 32-bit accumulators to support 16 16 32 or 32 32 48 operations ? cryptographic acceleration unit (cau) ? tightly-coupled coprocessor to accelerate software-based encrypt ion and message digest functions ? support for des, 3des, aes, md5, and sha-1 algorithms ? system debug support ? real-time trace for determin ing dynamic execution path ? background debug mode (bdm) for in-circuit debugging (debug_b+) ? real-time debug support, with six hardware breakpoints (4 pc, 1 address and 1 data) c onfigurable into a 1- or 2-level trigger ? on-chip memories ? up to 64-kbyte dual-ported sram on cpu internal bus, supporting core, dma, and usb access with standby power supply support for the first 16 kbytes ? up to 512 kbytes of interleaved flas h memory supporting 2-1-1-1 accesses ? power management ? fully static operation with processor sleep and whole chip stop modes ? rapid response to interrupts from th e low-power sleep mode (wake-up feature) ? clock enable/disable for each peripheral when not used (except backup watchdog timer) ? software controlled disable of external clock output for low-power consumption ? flexcan 2.0b module ? based on and includes all existing f eatures of the freescale toucan module ? full implementation of the can protocol specification version 2.0b ? standard data and remote frames (up to 109 bits long) ? extended data and remote frames (up to 127 bits long) ? zero to eight bytes data length ? programmable bit rate up to 1 mbit/sec ? flexible message buffers (mbs), totalling up to 16 mess age buffers of 0?8 byte data length each, configurable as rx or tx, all supporting standard and extended messages ? unused mb space can be used as general purpose ram space ? listen-only mode capability ? content-related addressing ? no read/write semaphores ? three programmable mask registers: global for mbs 0?13, special for mb14, and special for mb15 ? programmable transmit-first scheme: lo west id or lowest buffer number ? time stamp based on 16-bit free-running timer ? global network time, synchronized by a specific message ? maskable interrupts ? universal serial bus on-the-go (usb otg) dual-mode host and device controller ? full-speed / low-sp eed host controller ? usb 1.1 and 2.0 compliant full-s peed / low speed device controller ? 16 bidirectional end points because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 6 ? dma or fifo data stream interfaces ? low power consumption ? otg protocol logic ? fast ethernet controller (fec) ? 10/100 baset/tx capability, half duplex or full duplex ? on-chip transmit and receive fifos ? built-in dedicated dma controller ? memory-based flexible descriptor rings ? mini-flexbus ? external bus interface avai lable on 144 pin packages ? supports glueless interface with 8-bit rom/flash/sram/s imple slave peripherals. can address up to 2 mbytes of addresses ? 2 chip selects (fb_ cs [1:0]) ? non-multiplexed mode: 8-bit dedicated data bus, 20-bit address bus ? multiplexed mode: 16-bit data and 20-bit address bus ? fb_clk output to support synchronous memories ? programmable base address, size, and wait states to support slow peripherals ? operates at up to 40 mhz (bus clock) in 1:2 mode or up to 80 mhz (core clock) in 1:1 mode ? three universal asynchronous/synchr onous receiver transmitters (uarts) ? 16-bit divider for clock generation ? interrupt control logic with maskable interrupts ? dma support ? data formats can be 5, 6, 7 or 8 bits with even, odd, or no parity ? up to two stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (rts ) and clear-to-send (cts) lines for two uarts ? transmit and receive fifo buffers ?two i 2 c modules ? interchip bus interface for eeproms, lcd c ontrollers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master and slave modes support multiple masters ? automatic interrupt generation with programmable level ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfers ? up to three chip selects available ? master mode operation only ? programmable bit rates up to half the cpu clock frequency ? up to 16 pre-programmed transfers ? fast analog-to-digital converter (adc) ? eight analog input channels ? 12-bit resolution ? minimum 1.125 s conversion time ? simultaneous sampling of two channels for motor control applications ? single-scan or continuous operation ? optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 7 ? unused analog channels can be used as digital i/o ? four 32-bit timers with dma support ? 12.5 ns resolution at 80 mhz ? programmable sources for clock input, including an external clock option ? programmable prescaler ? input capture capability with programmable trigger edge on input pin ? output compare with programmable mode for the output pin ? free run and restart modes ? maskable interrupts on input capture or output compare ? dma trigger capability on input capture or output compare ? four-channel general purpose timer ? 16-bit architecture ? programmable prescaler ? output pulse-widths variable from microseconds to seconds ? single 16-bit input pulse accumulator ? toggle-on-overflow feature for pulse-width modulator (pwm) generation ? one dual-mode puls e accumulation channel ? pulse-width modulation timer ? support for pcm mode (resulting in superior signal quality compared to conventional pwm) ? operates as eight channels with 8-bit resolution or four channels with 16-bit resolution ? programmable period and duty cycle ? programmable enable/dis able for each channel ? software selectable polarity for each channel ? period and duty cycle are double buffered. change takes ef fect when the end of the current period is reached (pwm counter reaches zero) or when the channel is disabled. ? programmable center or left aligned outputs on individual channels ? four clock sources (a, b, sa, and sb) pr ovide for a wide range of frequencies ? emergency shutdown ? two periodic interrupt timers (pits) ? 16-bit counter ? selectable as free running or count down ? real-time clock (rtc) ? maintains system time-of-day clock ? provides stopwatch and alarm interrupt functions ? standby power supply (vstby) keeps the rtc running when the system is shut down ? software watchdog timer ? 32-bit counter ? low-power mode support ? backup watchdog timer (bwt) ? independent timer that can be used to help software recover from runaway code ? 16-bit counter ? low-power mode support ? clock generation features ? twelve to 48 mhz crystal, 8 mhz on-chip trimmed relaxatio n oscillator, or external oscillator reference options ? two to 10 mhz reference frequency for normal pll mode with a pre-divider programmable from 1 to 8 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 8 ? system can be clocked from pll or directly fr om crystal oscillator or relaxation oscillator ? low power modes supported ?2 n (n 0 15) low-power divider for extremely low frequency operation ? interrupt controller ? uniquely programmable vectors for all interrupt sources ? fully programmable level and priority for all peripheral interrupt sources ? seven external interrupt signals with fixed level and priority ? unique vector number fo r each interrupt source ? ability to mask any individual interrupt source or all interrupt sources (global mask-all) ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from low-power modes ? dma controller ? four fully programmable channels ? dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for 16-byte (4 32-bit) burst transfers ? source/destination address pointers th at can increment or remain constant ? 24-bit byte transfer counter per channel ? auto-alignment transfers support ed for efficient block movement ? bursting and cycle-steal support ? software-programmable dma requests for the uarts (3) and 32-bit timers (4) ? channel linking support ? reset ? separate reset in and reset out signals ? seven sources of reset: ? power-on reset (por) ? external ?software ? watchdog ? loss of clock / loss of lock ? low-voltage detection (lvd) ?jtag ? status flag indication of source of last reset ? chip configuration module (ccm) ? system configuration during reset ? selects one of six clock modes ? configures output pad drive strength ? unique part identification number and part revision number ? general purpose i/o interface ? up to 56 bits of general purpose i/o on 100-pin package ? up to 96 bits of general purpose i/o on 144-pin package ? bit manipulation supported via set/clear functions ? programmable drive strengths ? unused peripheral pins may be used as extra gpio ? jtag support for system level board testing because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 9 1.2.2 v2 core overview the version 2 coldfire processor core is comprised of two sepa rate pipelines decoupled by an in struction buffer. the two-stage instruction fetch pipeline (ifp) is responsible for instruction- address generation and instruction fetch. the instruction buffe r is a first-in-first-out (fifo) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (oep ). the oep includes two pipeline stages. the first stage decodes instructions and selects opera nds (dsoc); the second stage (agex) performs instruction ex ecution and calculates operand effective addresses, if needed. the v2 core implements the coldfire inst ruction set architecture revisi on a+ with support for a separate user stack pointer register and four new instructions to assi st in bit processing. additio nally, the core includes th e enhanced multiply-accumulat e (emac) unit for improved signal processing capabilities. the emac implements a three-stage arithmetic pipeline, optimized for 32x32 bit operations, with support for four 48-bit accumulato rs. supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete se t of instructions to process these data types. the emac provides support for execution of dsp operations within the context of a single processor at a minimal hardware cost. 1.2.3 integrated debug module the coldfire processor core debug interface is provided to support system debugging with low-cost debug and emulator development tools. through a standard debug interface, access to debug information and real-time tracing capability is provided on 144-lead packages. this allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators. the on-chip breakpoint resources include a to tal of nine programmable 32-bit registers: an address and an address mask register , a data and a data mask register, four pc registers, and on e pc mask register. these registers can be accessed through the dedicated debug serial communication channel or from the pro cessor?s supervisor mode progr amming model. the breakpoint registers can be configured to generate triggers by combining th e address, data, and pc conditions in a variety of single- or dual-level definitions. the trigger event can be programmed to ge nerate a processor halt or initiate a debug interrupt exceptio n. this device implements revision b+ of the coldfire debug architecture. the processor?s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interr upt event. this ensures the system cont inues to operate even during debugging. to support program trace, the v2 debug mo dule provides processor status (pst[3:0]) and debug data (d data[3:0]) ports. these buses and the pstclk output provid e execution status, captured operand data, and branch target addresses defining processor activity at the cpu?s clock rate. the device includes a new debug signal, allpst. this signal is the logical and of the processor status (pst[3:0]) signals and is useful for detecting when the pro cessor is in a halted st ate (pst[3:0] = 1111). the full debug/trace interface is available only on the 144-pin packages . however, every product features the dedicated debug serial communication cha nnel (dsi, dso, dsclk) and the allpst signal. 1.2.4 jtag the processor supports circuit board test strategies based on th e test technology committee of ieee and the joint test action group (jtag). the test logic includes a test access port (tap) co nsisting of a 16-state controller, an instruction register, an d three test registers (a 1-bit bypass register, a boundary-scan register, and a 32-bit id register). the boundary scan register links the device?s pins into one shift register. test logic, implemented using static logic design, is independent of the device syst em logic. the device implementation can: ? perform boundary-scan operations to te st circuit board electrical continuity ? sample system pins during operatio n and transparently shift out the re sult in the boundary scan register ? bypass the device for a given circuit board test by effectiv ely reducing the boundary-scan register to a single bit ? disable the output drive to pins during circuit-board testing ? drive output pins to stable levels because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 10 1.2.5 on-chip memories 1.2.5.1 sram the dual-ported sram module pr ovides a general-purpose 64-kbyte memory bl ock that the coldfire core can access in a single cycle. the location of the memory block can be set to any 64-kbyte boundary within the 4-gbyte address space. this memory is ideal for storing critical code or data structures and for use as the sy stem stack. because the sram module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module. the sram module is also accessible by th e dma, fec, and usb. the dual-ported nature of the sram makes it ideal for implementing applications with double-buffer schemes, where th e processor and a dma device operate in alternate regions of the sram to maximize system performance. 1.2.5.2 flash memory the coldfire flash module (cfm) is a non-volatile memory (n vm) module that connects to th e processor?s high-speed local bus. the cfm is constructed with four banks of 64-kbyte 16-bit flash memory arrays to generate 512 kbytes of 32-bit flash memory. these electrically erasable and programmable arrays serve as non-volatile program and data memory. the flash memory is ideal for program and data stor age for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. the cfm interfaces to the cold fire core through an optimized read-only memory controller that supports interleaved accesses from the 2-cycle flash memory arrays. a backdoor mapping of the flash memory is used for all program, erase, and verify operations, as well as providing a read datapath fo r the dma. flash memory may also be programmed via the ezport, which is a serial flash memory programming interface that allows the flash memory to be read, erased and programmed by an external controller in a format compatible wi th most spi bus flash memory chips. 1.2.6 cryptographic acceleration unit the mcf52235 device incorporates two hardware accelerators for cryptographic functions. first, the cau is a coprocessor tightly-coupled to the v2 coldfire core that implements a set of specialized operations to increase the throughput of software-based encryption and message digest functions, specifically the des, 3des, aes, md5 and sha-1 algorithms. second, a random number generator provides fips-140 compliant 32- bit values to security processing routines. both modules supply critical acceleration to software-based cryp tographic algorithms at a minimal hardware cost. 1.2.7 power management the device incorporates several low-power modes of operation entered under program control and exited by several external trigger events. an integrated power-on reset (por) circuit moni tors the input supply and forces an mcu reset as the supply voltage rises. the low voltage detector (lvd) monitors the suppl y voltage and is configurable to force a reset or interrupt condition if it falls below the lvd trip point. the ram standby switch provides power to ram when the supply voltage to the chip falls below the standby battery voltage. 1.2.8 flexcan the flexcan module is a communication controller implementing version 2.0 of the can protocol parts a and b. the can protocol can be used as an industrial control serial data bus , meeting the specific requirements of reliable operation in a har sh emi environment with high bandwidth. this instantiation of flexcan has 16 message buffers. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 11 1.2.9 mini-flexbus a multi-function external bus inte rface called the mini-flexbus is provided on the device with basic functionality of interfaci ng to slave-only devices with a maximum slave bus frequency up to 40 mhz in 1:2 mode and 80 mhz in 1:1 mode. it can be directly connected to the following asynchronous or sy nchronous devices with little or no additional circuitry: ? external roms ? flash memories ? programmable logic devices ? other simple target (slave) devices the mini-flexbus is a subset of the flexbus module fou nd on higher-end coldfire microprocessors. the mini-flexbus minimizes package pin-outs while maintaining a hi gh level of configurability and functionality. 1.2.10 usb on-the-go controller the device includes a universal serial bus on-the-go (usb ot g) dual-mode controller. usb is a popular standard for connecting peripherals and portable consumer electronic devices such as digital cameras and handheld computers to host pcs. the otg supplement to the usb specification extends usb to peer-to-peer application, enabling devices to connect directly to each other without the need for a pc . the dual-mode controller on the device can act as a usb otg host and as a usb device. it also supports fu ll-speed and low-speed modes. 1.2.11 fast ethernet controller (fec) the ethernet media access controller (mac) supports 10 and 10 0 mbps ethernet/ieee 802.3 networ ks. an external transceiver interface and transceiver functio n are required to complete the interface to the media. the fec supports three different standa rd mac-phy (physical) interfaces for connection to an ex ternal ethernet transceiver. the fecs supports the 10/100 mbps mii, and the 10 mbps-only 7-wire interface. 1.2.12 uarts the device has three full-duplex uarts that function independently. the three uarts can be clocked by the system bus clock, eliminating the need for an external cloc k source. on smaller packages, the third uart is multiplexed with other digital i/o functions. 1.2.13 i 2 c bus the processor includes two i 2 c modules. the i 2 c bus is an industry-standard, two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. this bus is suitable for applications requiring occasional communications over a short distance between many devices. 1.2.14 qspi the queued serial peripheral interface (qsp i) provides a synchronous se rial peripheral interface with queued transfer capabilit y. it allows up to 16 transfers to be queued at once, mi nimizing the need for cpu in tervention between transfers. 1.2.15 fast adc the fast adc consists of an eight-channel input select multip lexer and two independent sample and hold (s/h) circuits feeding separate 12-bit adcs. the two separate converters store their results in accessible buffers for further processing. signals on the synca and syncb pins initiate an adc conversion. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 12 the adc can be configured to perform a single scan and halt, a scan when triggered, or a progr ammed scan sequence repeatedly until manually stopped. the adc can be configured for sequential or simultaneous conversion. when configured fo r sequential conversions, up to eight channels can be sampled and stored in an y order specified by the channel list register. both adcs may be required during a scan, depending on the inputs to be sampled. during a simultaneous conversion, both s/ h circuits are used to capture two diff erent channels at the same time. this configuration requires that a single channel may no t be sampled by both s/h circuits simultaneously. optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limi t registers) or at several diff erent zero crossing conditions. 1.2.16 dma timers (dtim0?dtim3) there are four independent, dma transfer capable 32-bit timers (dtim0, dtim1, dtim2, and dtim3) on the device. each module incorporates a 32-bit timer with a separate register set for configuration and control. the timers can be configured to operate from the system clock or from an external clock source using one of the dtin n signals. if the system clock is selected, it can be divided by 16 or 1. the input clock is further divide d by a user-programmable 8-bit pr escaler that clocks the actual timer counter register (tcr n ). each of these timers can be configured for input capture or reference (output) compare mode. timer events may optionally cause in terrupt requests or dma transfers. 1.2.17 general purpose timer (gpt) the general purpose timer (gpt) is a four-channel timer modul e consisting of a 16-bit programmable counter driven by a seven-stage programmable prescaler. each of the four channels can be configured for input capture or output compare. additionally, channel th ree, can be configured as a pulse accumulator. a timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. the input capture and output compare functions allow simulta neous input waveform measurements and output waveform generation. the input capture function can capture the time of a selected transition edge. th e output compare function can generate output waveforms and timer software delays. the 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator. 1.2.18 periodic interrupt timers (pit0 and pit1) the two periodic interrupt timers (pit0 and pit1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. e ach timer can count down from the value written in its pit modulus register or it can be a free-runnin g down-counter. 1.2.19 real-time clock (rtc) the real-time clock (rtc) module maintains the system (time- of-day) clock and provides stopwatch, alarm, and interrupt functions. it includes full clock features: seconds, minutes, hour s, days and supports a host of time-of-day interrupt function s along with an alarm interrupt. 1.2.20 pulse-width modulation (pwm) timers the device has an 8-channel, 8-bit pwm tim er. each channel has a programmable period and duty cycle as well as a dedicated counter. each of the modulator s can create independent continuous waveforms wi th software-selectable duty rates from 0% to 100%. the timer supports pcm mode, which results in superior si gnal quality when compared to that of a conventional pwm. the pwm outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. for because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 13 higher period and duty cycle reso lution, each pair of adjacent channels ([7:6], [5 :4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. the module can, therefore, be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels . 1.2.21 software watchdog timer the watchdog timer is a 32-bit timer that facilitates recove ry from runaway code. the watchdog counter is a free-running down-counter that generates a reset on underflow. to prevent a reset, software must periodically restart the countdown. 1.2.22 backup watchdog timer the backup watchdog timer is an independent 16-bit timer that, like the software watchdog timer , facilitates recovery from runaway code. this timer is a free-running down-counter that gene rates a reset on underflow. to prevent a reset, software must periodically restart the countdown. the backup watchdog timer can be clocked by either the relaxation oscillator or the system clock. 1.2.23 phase-locked loop (pll) the clock module contains a crystal oscillator, 8 mhz on-chip re laxation oscillator (oco), phase-locked loop (pll), reduced frequency divider (rfd), low-power divide r status/control registers, and control logic. to improve noise immunity, the pll, crystal oscillator, and relaxation oscilla tor have their own power supply inputs: vddpll and vsspll. all other circuits are powered by the normal supply pins, vdd and vss. 1.2.24 interrupt controllers (intc n ) the device has two interrupt controllers that supports up to 128 interrupt sources. there ar e 56 programmable sources, 49 of which are assigned to unique peripheral interrupt requests. the remaining seven sources are unassigned and may be used for software interrupt requests. 1.2.25 dma controller the direct memory access (dma) controller provides an efficient way to move blocks of data with minimal processor intervention. it has four channels that allow byte, word, longw ord, or 16-byte burst line transf ers. these transfers are trigge red by software explicitly setting a dcr n [start] bit or by the occurrence of certain uart or dma timer events. 1.2.26 reset the reset controller determines the source of reset, asserts the approp riate reset signals to the system, and keeps track of wh at caused the last reset. there are seven sources of reset: ? external reset input ? power-on reset (por) ? watchdog timer ? phase locked-loop (pll) loss of lock / loss of clock ?software ? low-voltage detector (lvd) ?jtag control of the lvd and its associated rese t and interrupt are managed by the reset cont roller. other registers provide status f lags indicating the last source of reset and a cont rol bit for software assertion of the rsto pin. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 14 1.2.27 gpio nearly all pins on the device have general purpose i/o capabi lity and are grouped into 8-bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pin. 1.2.28 part numbers and packaging this product is rohs-compliant. refer to the product page at freescale.com or contact your sales office for up-to-date rohs information. table 2. orderable part number summary freescale part number flexcan encryption speed (mhz) flash (kbytes) sram (kbytes) package temp range ( c) mcf52252af80 ? ? 80 256 32 100 lqfp 0 to +70 mcf52252caf66 ? ? 66 -40 to +85 mcf52254af80 ? ? 80 512 64 100 lqfp 0 to +70 mcf52254caf66 ? ? 66 -40 to +85 mcf52255caf80 ?? 80 512 64 100 lqfp -40 to +85 MCF52256AG80 ? ? 80 256 32 144 lqfp 0 to +70 mcf52256cag66 ? ? 66 64 -40 to +85 mcf52256cvn66 ? ?6 6 6 4 144 mapbga -40 to +85 mcf52256vn80 ? ? 80 32 0 to +70 mcf52258ag80 ? ? 80 512 64 144 lqfp 0 to +70 mcf52258cag66 ? ? 66 -40 to +85 mcf52258cvn66 ? ?6 6 144 mapbga -40 to +85 mcf52258vn80 ? ? 80 0 to +70 mcf52259cag80 ?? 80 512 64 144 lqfp -40 to +85 mcf52259cvn80 ?? 144 mapbga -40 to +85 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 15 figure 2 shows the pinout configuration for the 144 lqfp. figure 2. 144 lqfp pin assignment clkmod1 clkmod0 rstout rstin fb_d5 fb_d6 fb_d7 fb_oe fb_a15 vdd vss fb_a16 fb_a17 fb_a18 fb_a19 irq3 irq5 fec_rxd3 fec_rxd2 vdd vss fec_rxd1 fec_rxd0 fec_rxdv fec_rxclk fec_rxer fec_txer fec_txclk fec_txen vdd vss fec_txd0 fec_txd1 fec_txd2 fec_txd3 fec_col ? 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 fb_d4 1 108 fec_crs fb_a14 2 107 vddpll fb_a13 3 106 extal fb_a12 4 105 xtal fb_a11 5 104 vsspll fb_a10 6 103 irq1 vdd 7 102 urxd2 vss 8 101 utxd2 test 9 100 vdd rcon 10 99 vss tin0 11 98 urts2 tin1 12 97 ucts2 rtc_extal 13 96 irq7 rtc_xtal 14 95 icoc2 ucts0 15 94 icoc1 utxd0 16 93 icoc0 urxd0 17 92 vdd urts0 18 91 vss tin3 19 90 pst0 vdd 20 89 pst1 vss 21 88 pst2 pcs3 22 87 pst3 pcs2 23 86 ddata3 qsdi 24 85 ddata2 qsd0 25 84 ddata1 sck 26 83 ddata0 pcs0 27 82 vssusb scl 28 81 usb_dp sda 29 80 usb_dm vdd 30 79 vddusb vss 31 78 vstby fb_a9 32 77 an4 fb_a8 33 76 an5 fb_a7 34 75 an6 fb_a6 35 74 an7 fb_a5 36 73 vdda 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 fb_ale tms trst tdi tdo allpst tclk jtag_en fb_rw fb_d3 fb_d2 vdd vss fb_d1 fb_d0 fb_cs0 fb_a4 fb_a3 fb_a2 fb_a1 fb_a0 icoc3 vdd vss ucts1 utxd1 urxd1 urts1 tin2 an0 an1 an2 an3 vssa vrl vrh because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 family configurations freescale semiconductor 16 figure 3 shows the pinout configuration for the 100 lqfp. figure 3. 100 lqfp pin assignments an5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 v dd v ss test rcon tin0 tin1 rtc_xtal ucts0 utxd0 urxd0 urts0 tin3 v dd v ss pcs3 pcs2 qsdi qsdo sck pcs0 scl sda v dd 100 lqfp 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 fec_crs v ddpll extal xtal v sspll irq1 urxd2 utxd2 v dd v ss urts2 ucts2 irq7 icoc2 icoc1 icoc0 v ss usb usb_dp usb_dm v dd usb v stby an6 an7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 clkmod1 clkmod0 rstout rst in irq3 irq 5 fec_rxd3 fec_rxd2 v dd v ss fec_rxd1 fec_rxd0 fec_rxdv fec_rxclk fec_rxer fec_txclk fec_txen v dd v ss fec_txd0 fec_txd1 fec_txd2 fec_txd3 fec_col 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 tms trst tdi tdo allpst tclk jtag_en v dd v ss icoc3 v dd v ss ucts1 utxd1 urxd1 urts1 tin2 an0 an1 an2 an3 v ssa v rl v rh v dda v ss rtc_extal an4 fec_txer because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 17 figure 4 shows the pinout configuration for the 144 mapbga. 123456789101112 a vss rstout rstin fb_d6 fb_d7 irq3 irq5 fec_ rxd0 fec_ rxer fec_ txen fec_ txd3 vss a b test fb_a14 fb_d4 fb_d5 fb_oe fb_a19 fec_ rxd1 fec_ rxclk fec_ txclk fec_ txd2 fec_col fec_crs b c tin1 fb_a12 fb_a13 fb_a15 fb_a16 fb_a18 fec_ rxd2 fec_ rxdv fec_ txd1 urxd2 vddpll extal c d rtc_ extal tin0 fb_a11 clkmod1 clkmod0 fb_a17 fec_ rxd3 fec_ txer fec_ txd0 utxd2 vsspll xtal d e rtc_ xtal ucts0 fb_a10 rcon vdd vdd vdd vdd irq1 urts2 ucts2 irq7 e f utxd0 urxd0 urts0 tin3 vdd vss vss vss pst3 ddata0 ddata1 icoc0 f g qsdo qsdi pcs2 pcs3 vdd vss vss vss ddata3 pst2 pst1 pst0 g h scl sda sck pcs0 vdd vdd vdd vss vssusb ddata2 usb_dm usb_dp h j fb_a6 fb_a7 fb_a9 fb_a8 fb_d0 fb_a3 vdd tin2 vddusb icoc2 icoc1 vstby j ktms trst fb_ale fb_a5 fb_d2 fb_a4 ucts1 utxd1 an3 an6 an4 an5 k l tdi tdo allpst fb_d3 fb_d1 fb_a1 fb_a0 urxd1 an2 vrh vdda an7 l m vss jtag_ en tclk fb_rw fb_cs0 fb_a2 icoc3 urts1 an0 an1 vrl vssa m 123456789101112 figure 4. pinout top view (144 mapbga) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 18 family configurations table 3 shows the pin functions by primary a nd alternate purpose, and illustrate s which packages contain each pin. table 3. pin functions by primary and alternate purpose pin group primary function secondary function (alt 1) tertiary function (alt 2) quaternary function (gpio) slew rate drive strength/co ntrol 1 pull-up/ pull-down 2 pin on 144 mapbga pin on 144 lqfp pin on 100 lqfp adc an[7:0] ? ? pan[7:0] low low ? l12, k10, k12, k11, k9, l9, m10, m9 74?77; 69, 68, 67 ,66 51?54, 46, 45, 44, 43 vdda ? ? ? n/a n/a ? l11 73 50 vssa ? ? ? n/a n/a ? m12 70 47 vrh ? ? ? n/a n/a ? l10 72 49 vrl ? ? ? n/a n/a ? m11 71 48 clock generation extal ? ? ? n/a n/a ? c12 106 73 xtal ? ? ? n/a n/a ? d12 105 72 vddpll ? ? ? n/a n/a ? c11 107 74 vsspll ? ? ? n/a n/a ? d11 104 71 rtc rtc_extal ? ? ? n/a n/a ? d1 13 7 rtc_xtal ? ? ? n/a n/a ? e1 14 8 debug data allpst ? ? ? low high ? l3 42 30 ddata[3:0] ? ? pdd[7:4] lo w high ? g9, h10, f11, f10 86, 85, 84, 83 ? pst[3:0] ? ? pdd[3:0] low high ? f9, g10, g11, g12 87?90 ? because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 19 fec fec _ col ? ? pti0 psrrh[0] pdsrh[0] ? b11 109 76 fec_ crs ? ? pti1 psrrh[1] pdsrh[1] ? b12 108 75 fec _ rxclk ? ? pti2 psrrh[2] pdsrh[2] ? b8 120 87 fec _ rxd[3:0] ? ? pti[6:3] psrrh[ 6:3] pdsrh[6:3] ? d7, c7 , b7, a8 127, 126, 123, 122 94, 93, 90, 89 fec _ rxdv ? ? pti7 psrrh[7] pdsrh[7] ? c8 121 88 fec_ rxer ? ? ptj0 psrrh[8] pdsrh[8] ? a9 119 86 fec _ txclk ? ? ptj1 psrrh[9] pdsrh[9] ? b9 117 84 fec _ txd[3:0] ? ? ptj[5:2] psrrh[13:10] pdsrh[13:1 0] ? a11, b10, c9, d9 110?113 77, 78, 79, 80 fec fec _ txen ? ? ptj6 psrrh[14] pdsrh[14] ? a10 116 83 fec _ txer ? ? ptj7 psrrh[15] pdsrh[15] ? d8 118 85 i 2 c0 3 i2c_scl0 ? utxd2 pas0 psrr[0] pdsr[0] pull-up 4 h1 28 22 i2c_sda0 ? urxd2 pas1 psrr[0] pdsr[0] pull-up 4 h2 29 23 interrupts irq7 ? ? pnq7 low low pull-up 4 e12 96 63 irq5 fec_mdc ? pnq5 low low pull-up 4 a7 128 95 irq3 fec_mdio ? pnq3 low low pull-up 4 a6 129 96 irq1 ? usb_alt clk pnq1 low high pull-up 4 e9 103 70 jtag/bdm jtag_en ? ? ? n/a n/a pull-down m2 44 32 tclk/ pstclk/ clkout ?fb_clk ? low low pull-up 5 m3 43 31 tdi/dsi ? ? ? n/a n/a pull-up 5 l1 40 28 tdo/dso ? ? ? low low ? l2 41 29 tms/bkpt ? ? ? n/a n/a pull-up 5 k1 38 26 trs t /dsclk ? ? ? n/a n/a pull-up 5 k2 39 27 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function (alt 1) tertiary function (alt 2) quaternary function (gpio) slew rate drive strength/co ntrol 1 pull-up/ pull-down 2 pin on 144 mapbga pin on 144 lqfp pin on 100 lqfp because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 20 family configurations mode selection rcon /e zpcs ? ? ? n/a n/a pull-up e4 10 4 clkmod[1:0] ? ? ? n/a n/a pull-down d4, d5 144, 143 100, 99 qspi qspi_cs3 synca usb_dp_ pdown pqs6 psrr[7] pdsr[7] ? g4 22 16 qspi_cs2 syncb usb_dm _ pdown pqs5 psrr[6] pdsr[6] ? g3 23 17 qspi_cs0 i2c_sda0 ucts1 pqs3 psrr[4] pdsr[4] pull-up 6 h4 27 21 qspi_clk/ ezpck i2c_scl0 urts1 pqs2 psrr[3] pdsr[3] pull-up 6 h3 26 20 qspi qspi_din/ ezpd i2c_sda1 urxd1 pqs1 psrr[2] pdsr[2] pull-up 6 g2 24 18 qspi_dout/e zpq i2c_scl1 utxd1 pqs0 psrr[1] pdsr[1] pull-up 6 g1 25 19 reset 7 rsti ? ? ? n/a n/a pull-up 7 a3 141 97 rsto ? ? ? low high ? a2 142 98 test test ? ? ? n/a n/a pull-down b1 9 3 timer 3, 16-bit gpt3 ? pwm7 pta3 psrr[23] pdsr[23] pull-up 8 m7 58 35 timer 2, 16-bit gpt2 ? pwm5 pta2 psrr[22] pdsr[22] pull-up 8 j10 95 62 timer 1, 16-bit gpt1 ? pwm3 pta1 psrr[21] pdsr[21] pull-up 8 j11 94 61 timer 0, 16-bit gpt0 ? pwm1 pta0 psrr[20] pdsr[20] pull-up 8 f12 93 60 timer 3, 32-bit dtin3 dtout3 pwm6 ptc3 psrr[19] pdsr[19] ? f4 19 13 timer 2, 32-bit dtin2 dtout2 pwm4 ptc2 psrr[18] pdsr[18] ? j8 65 42 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function (alt 1) tertiary function (alt 2) quaternary function (gpio) slew rate drive strength/co ntrol 1 pull-up/ pull-down 2 pin on 144 mapbga pin on 144 lqfp pin on 100 lqfp because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 21 timer 1, 32-bit dtin1 dtout1 pwm2 ptc1 psrr[17] pdsr[17] ? c1 12 6 timer 0, 32-bit dtin0 dtout0 pwm0 ptc0 psrr[16] pdsr[16] ? d2 11 5 uart 0 ucts0 ? usb_vbu se pua3 psrr[11] pdsr[11] ? e2 15 9 urts0 ? usb_vbu sd pua2 psrr[10] pdsr[10] ? f3 18 12 urxd0 ? ? pua1 psrr[9] pdsr[9] ? f2 17 11 utxd0 ? ? pua0 psrr[8] pdsr[8] ? f1 16 10 uart 1 ucts1 synca urxd2 pub3 psrr[15] pdsr[15] ? k7 61 38 urts1 syncb utxd2 pub2 psrr[14] pdsr[14] ? m8 64 41 urxd1 i2c_sda1 ? pub1 psrr[13] pdsr[13] pull-up 6 l8 63 40 utxd1 i2c_scl1 ? pub0 psrr[12] pdsr[12] pull-up 6 k8 62 39 uart 2 ucts2 i2c_scl1 usb_ vbusch g puc3 psrr[27] pdsr[27] pull-up 6 e11 97 64 urts2 i2c_sda1 usb_ vbusdis puc2 psrr[26] pdsr[26] pull-up 6 e10 98 65 urxd2 canrx ? puc1 psrr[25] pdsr[25] ? c10 102 69 utxd2 cantx ? puc0 psrr[24] pdsr[24] ? d10 101 68 usb otg usb_dm ? ? ? n/a n/a ? h11 80 57 usb_dp ? ? ? n/a n/a ? h12 81 58 usb_vdd ? ? ? n/a n/a ? j9 79 56 usb_vss ? ? ? n/a n/a ? h9 82 59 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function (alt 1) tertiary function (alt 2) quaternary function (gpio) slew rate drive strength/co ntrol 1 pull-up/ pull-down 2 pin on 144 mapbga pin on 144 lqfp pin on 100 lqfp because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 22 family configurations mini- flexbus 9 fb_ale fb_cs1 ? pas2 psrrl[20] pdsrl[20] ? k3 37 ? fb_ad[7:0] ? ? pte[7:0] psrrl[7:0] pdsrl[7:0] ? j2, j1, k4, k6, j6, m6, l6, l7 34?36; 53?57 ? fb_ad[15:8] ? ? ptf[7:0] psrrl[15:8] pdsrl[15:8] ? c4, b2, c3, c2, d3, e3, j3, j4 136, 2?6, 32?33 ? fb_ad[19:16] ? ? ptg[3:0] psrrl[19:16] pdsrl[19:16 ] ? b6, c6, d6, c5 130?133 ? fb_cs0 ? ? ptg5 psrrl[21] pdsrl[21] ? m5 52 ? fb_r/w ? ? ptg7 psrrl[31] pdsrl[31] ? m4 45 ? fb_oe ? ? ptg6 psrrl[30] pd srl[30] ? b5 137 ? fb_d7 canrx ? pth5 psrrl[29] pdsrl[29] ? a5 138 ? fb_d6 cantx ? pth4 psrrl[28] pdsrl[28] ? a4 139 ? fb_d5 i2c_scl1 ? pth3 psrrl[27] pdsrl[27] pull-up 6 b4 140 ? fb_d4 i2c_sda1 ? pth2 psrrl[26] pdsrl[26] pull-up 6 b3 1 ? fb_d3 usb_ vbusd ? pth1 psrrl[25] pdsrl[25] ? l4 46 ? fb_d2 usb_ vbuse ? pth0 psrrl[24] pdsrl[24] ? k5 47 ? fb_d1 synca ? pth7 psrrl[23] pdsrl[23] ? l5 50 ? fb_d0 syncb ? pth6 psrrl[22] pdsrl[22] ? j5 51 ? standby voltage vstby ? ? ? n/a n/a ? j12 78 55 vdd 10 vdd ? ? ? n/a n/a ? e5?e8; f5; g5; h5?7; j7 7; 20; 30; 48; 59; 92; 100; 115; 125; 135 1; 14; 24; 33; 36; 67; 82; 92 table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function (alt 1) tertiary function (alt 2) quaternary function (gpio) slew rate drive strength/co ntrol 1 pull-up/ pull-down 2 pin on 144 mapbga pin on 144 lqfp pin on 100 lqfp because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
family configurations mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 23 vss vss ? ? ? n/a n/a ? a1; a12; f6?8; g6?8; h8; m1 8; 21; 31; 49; 60; 91; 99; 114; 124; 134 2; 15; 25; 34; 37; 66; 81; 91 1 the pdsr and pssr registers are part of the gpio module. all programmable signals default to 2ma drive in normal (single-chip) mode. 2 all signals have a pull-up in gpio mode. 3 i 2 c1 is multiplexed with specific pins of the qspi, uart1, uart2, and mini-flexbus pin groups. 4 for primary and gpio functions only. 5 only when jtag mode is enabled. 6 for secondary and gpio functions only. 7 rsti has an internal pull-up resistor; however, the use of an external resistor is strongly recommended. 8 for gpio functions, the primary function has pull-up control within the gpt module. 9 available on 144-pin packages only. 10 this list for power and ground does not include those dedicated powe r/ground pins included elsewhere, such as in the adc, usb, and pll. table 3. pin functions by primary and alternate purpose (continued) pin group primary function secondary function (alt 1) tertiary function (alt 2) quaternary function (gpio) slew rate drive strength/co ntrol 1 pull-up/ pull-down 2 pin on 144 mapbga pin on 144 lqfp pin on 100 lqfp because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 24 2 electrical characteristics this section contains electrical specification tables and refere nce timing diagrams for the microcontroller unit, including detailed information on power considerations, dc/ac electrical characteristics, a nd ac timing specifications. note the parameters specified in this data sheet supersede any values found in the module specifications. 2.1 maximum ratings table 4. absolute maximum ratings 1, 2 1 functional operating conditions are given in dc el ectrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. 2 this device contains circuitry protecting against dam age due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (v ss or v dd ). rating symbol value unit supply voltage v dd ?0.3 to + 4.0 v clock synthesizer supply voltage v ddpll ?0.3 to + 4.0 v ram standby supply voltage v stby +1.8 to 3.5 v usb standby supply voltage v ddusb ?0.3 to + 4.0 v digital input voltage 3 3 input must be current limited to the i dd value specified. to determine the value of the required current-limiting resistor, calculat e resistance values for positive and negative clamp voltages, then use the larger of the two values. v in ?0.3 to + 4.0 v extal pin voltage v extal 0 to 3.3 v xtal pin voltage v xtal 0 to 3.3 v instantaneous maximum current single pin limit (applies to all pins) 4, 5 4 all functional non-supply pins are internally clamped to v ss and v dd . 5 the power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in the external power supply going out of regulation. ensure that the external v dd load shunts current greater than maximum injection current. this is the greatest risk when the mcu is not consuming power (e.g., no clock). i dd 25 ma operating temperature range (packaged) t a (t l - t h ) ?40 to 85 or 0 to 70 6 6 depending on the packaging; see the orderable part number summary. c storage temperature range t stg ?65 to 150 c because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 25 2.2 current consumption table 5. typical active curren t consumption specifications characteristic symbol typical 1 active (sram) 1 tested at room temperature with cpu polling a status register. all clocks were off except the uart and cfm (when running from flash memory). typical 1 active (flash) peak 2 (flash) 2 peak current measured with all modules active, cpu polling a status register, and default drive strength with matching load. unit pll @ 8 mhz i dd 22 30 36 ma pll @ 16 mhz 31 45 60 pll @ 64 mhz 84 100 155 pll @ 80 mhz 102 118 185 ram standby supply current ? normal operation: v dd > v stby - 0.3 v ? standby operation: v dd < v ss + 0.5 v i stby ? ? 5 20 a a analog supply current ? normal operation i dda 2 3 3 tested using auto power down (apd), which powers down the adc between conversions; adc running at 4 mhz in once parallel mode with a sample rate of 3 khz. 15 ma usb supply current i ddusb ?2m a pll supply current i ddpll ?6 4 4 tested with the pll mfd set to 7 (max value). setting the mf d to a lower value results in lower current consumption. ma table 6. current consumption in low-power mode, code from flash memory 1,2,3 1 all values are measured with a 3.30v power supply. tests performed at room temperature. 2 refer to the power management chapter in the mcf52259 reference manual for more information on low-power modes. 3 clkout, pst/ddata signals, and all peripheral clocks except uart0 and cfm off before entering low-power mode. clkout is disabled. mode 8 mhz (typ) 16 mhz (typ) 64 mhz (typ) 80 mhz (typ) unit symbol stop mode 3 (stop 11) 4 4 see the description of the low-power control register (lpcr) in the mcf52259 reference manual for more information on stop modes 0?3. 0.150 ma i dd stop mode 2 (stop 10) 4 7.0 stop mode 1 (stop 01) 4,5 5 results are identical to stop 00 for typical values be cause they only differ by clkout power consumption. clkout is already disabled in this instance prior to entering low-power mode. 9 1 01 51 7 stop mode 0 (stop 00) 5 9 1 01 51 7 wait / doze 21 32 56 65 r u n 2 33 67 08 1 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 26 2.3 thermal characteristics table 8 lists thermal resistance values. table 7. current consumption in low-power mode, code from sram 1,2,3 1 all values are measured with a 3.30v power supply. tests performed at room temperature. 2 refer to the power management chapter in the mcf52259 reference manual for more information on low-power modes. 3 clkout, pst/ddata signals, and all peripheral clocks except uart0 off before entering low-power mode. clkout is disabled. code executed from sram with fl ash memory shut off by writing 0x0 to the flashbar register. mode 8 mhz (typ) 16 mhz (typ) 64 mhz (typ) 80 mhz (typ) unit symbol stop mode 3 (stop 11) 4 4 see the description of the low-power control register (lpcr) in the mcf52259 reference manual for more information on stop modes 0?3. 0.090 ma i dd stop mode 2 (stop 10) 4 7 stop mode 1 (stop 01) 4,5 5 results are identical to stop 00 for typical values be cause they only differ by clkout power consumption. clkout is already disabled in this instance prior to entering low-power mode. 9 1 01 51 7 stop mode 0 (stop 00) 5 9 1 01 51 7 wait / doze 13 18 42 50 r u n 1 62 15 56 5 table 8. thermal characteristics characteristic symbol value unit 144 mapbga junction to am bient, natural convection single layer board (1s) ja 53 1,2 c / w junction to ambient, natural convection four layer board (2s2p) ja 30 1,3 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 43 1,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 26 1,3 c / w junction to board ? jb 16 4 c / w junction to case ? jc 9 5 c / w junction to top of package natural convection jt 2 6 c / w maximum operating junction temperature ? t j 105 o c 144 lqfp junction to ambient, natural convection single layer board (1s) ja 44 7,8 c / w junction to ambient, natural convection four layer board (2s2p) ja 35 1,9 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 35 1,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 29 1,3 c / w junction to board ? jb 23 10 c / w junction to case ? jc 7 11 c / w junction to top of package natural convection jt 2 12 c / w maximum operating junction temperature ? t j 105 o c because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 27 100 lqfp junction to ambient, natural convection single layer board (1s) ja 53 13,14 c / w junction to ambient, natural convection four layer board (2s2p) ja 39 1,15 c / w junction to ambient, (@200 ft/min) single layer board (1s) jma 42 1,3 c / w junction to ambient, (@200 ft/min) four layer board (2s2p) jma 33 1,3 c / w junction to board ? jb 25 16 c / w junction to case ? jc 9 17 c / w junction to top of package natural convection jt 2 18 c / w maximum operating junction temperature ? t j 105 o c 1 ja and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation specifications in th e system design to prevent device junction temperatures from exceeding the rated specification. system designers should be aw are that device junction temperatures can be significantly influenced by board la yout and surrounding devices. conformanc e to the device junction temperature specification can be verified by physical meas urement in the custom er?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 3 per jedec jesd51-6 with the board jesd51-7) horizontal. 4 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). 6 thermal characterization parameter indicating the temper ature difference between package top and the junction temperature per jedec jesd51-2. when gree k letters are not available, the therma l characterization parameter is written in conformance with psi-jt. 7 ja and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation specifications in th e system design to prevent device junction temperatures from exceeding the rated specification. system designers should be aw are that device junction temperatures can be significantly influenced by board la yout and surrounding devices. conformanc e to the device junction temperature specification can be verified by physical meas urement in the custom er?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 8 per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 9 per jedec jesd51-6 with the board jesd51-7) horizontal. 10 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 11 thermal resistance between the die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). 12 thermal characterization parameter indicating the temper ature difference between package top and the junction temperature per jedec jesd51-2. when gree k letters are not available, the therma l characterization parameter is written in conformance with psi-jt. 13 ja and jt parameters are simulated in conformance with eia/j esd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation specifications in th e system design to prevent device junction temperatures from exceeding the rated specification. system designers should be aw are that device junction temperatures can be significantly influenced by board la yout and surrounding devices. conformanc e to the device junction temperature specification can be verified by physical meas urement in the custom er?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 14 per jedec jesd51-2 with the single-layer board (jesd51-3) horizontal. 15 per jedec jesd51-6 with the board jesd51-7) horizontal. table 8. thermal characteristics (continued) characteristic symbol value unit because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 28 2.4 flash memory characteristics the flash memory charact eristics are shown in table 9 and table 10 . 16 thermal resistance between the die and the printed circ uit board in conformance with jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 17 thermal resistance between the die and the case top surface as measured by the cold plate me thod (mil spec-883 method 1012.1). 18 thermal characterization parameter indicating the temper ature difference between package top and the junction temperature per jedec jesd51-2. when gree k letters are not available, the therma l characterization parameter is written in conformance with psi-jt. the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = chip internal power, i dd v dd , watts p i/o = power dissipation on input and output pins ? user determined, watts for most applications p i/o < p int and can be ignored. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + jma p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equat ions (1) and (2) iteratively for any value of t a . table 9. sgfm flash program and erase characteristics (v dd = 3.0 to 3.6 v) parameter symbol min typ max unit system clock (read only) f sys(r) 0? 66.67 or 80 1 1 depending on packaging; see the orderable part number summary. mhz system clock (program/erase) 2 2 refer to the flash memory section for more information f sys(p/e) 0.15 ? 66.67 or 80 1 mhz table 10. sgfm flash module life characteristics (v dd = 3.0 to 3.6 v) parameter symbol value unit maximum number of guaranteed program/erase cycles 1 before failure 1 a program/erase cycle is defined as switching the bits from 1 0 1. p/e 10,000 2 cycles data retention at average operating temperature of 85 c retention 10 years t j t a p d jma () += p d kt j 273 + () = because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 29 2.5 ezport electrical specifications 2.6 esd protection 2 reprogramming of a flash memory array block prior to erase is not required. table 11. ezport electrical specifications name characteristic min max unit ep1 epck frequency of operation (all commands except read) ? f sys / 2 mhz ep1a epck frequency of operation (read command) ? f sys / 8 mhz ep2 epcs_b negation to next epcs_b assertion 2 t cyc ?ns ep3 epcs_b input valid to epck high (setup) 5 ? ns ep4 epck high to epcs_b input invalid (hold) 5 ? ns ep5 epd input valid to epck high (setup) 2 ? ns ep6 epck high to epd input invalid (hold) 5 ? ns ep7 epck low to epq output valid (out setup) ? 12 ns ep8 epck low to epq output invalid (out hold) 0 ? ns ep9 epcs_b negation to epq tri-state ? 12 ns table 12. esd protection characteristics 1, 2 1 all esd testing is in conformity with cdf -aec-q100 stress test qualification for automotive grade integrated circuits. 2 a device is defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and functional testing is performed per applicable device spec ification at room temperature followed by hot temperature, unless specified othe rwise in the device specification. characteristics symbol value units esd target for human body model hbm 2000 v esd target for machine model mm 200 v hbm circuit description r series 1500 c 100 pf mm circuit description r series 0 c 200 pf number of pulses per pin (hbm) ? positive pulses ? negative pulses ? ? 1 1 ? number of pulses per pin (mm) ? positive pulses ? negative pulses ? ? 3 3 ? interval of pulses ? 1 sec because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 30 2.7 dc electrical specifications table 13. dc electrical specifications 1 1 refer to ta b l e 1 4 for additional pll specifications. characteristic symbol min max unit supply voltage v dd 3.0 3.6 v standby voltage v stby 1.8 3.5 v input high voltage v ih 0.7 v dd 4.0 v input low voltage v il v ss ? 0.3 0.35 v dd v input hysteresis 2 2 only for pins: irq1, irq3. irq5, irq7, rstin_b, test, rcon_b, pcs0 , sck, i2c_sda, i2c_scl, tclk, trst_b v hys 0.06 v dd ?mv low-voltage detect trip voltage (v dd falling) v lvd 2.15 2.3 v low-voltage detect hysteresis (v dd rising) v lv d h y s 60 120 mv input leakage current v in = v dd or v ss , digital pins i in ?1.0 1.0 a output high voltage (all inpu t/output and all output pins) i oh = ?2.0 ma v oh v dd ? 0.5 ? v output low voltage (all input/ output and all output pins) i ol = 2.0ma v ol ?0 . 5v output high voltage (high drive) i oh = -5 ma v oh v dd ? 0.5 ? v output low voltage (high drive) i ol = 5 ma v ol ?0 . 5v output high voltage (low drive) i oh = -2 ma v oh v dd - 0.5 ? v output low voltage (low drive) i ol = 2 ma v ol ?0 . 5v weak internal pull up device current, tested at v il max. 3 3 refer to ta b l e 3 for pins having internal pull-up devices. i apu ?10 ?130 a input capacitance 4 ? all input-only pins ? all input/output (three-state) pins 4 this parameter is characterized before qualification rather than 100% tested. c in ? ? 7 7 pf because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 31 2.8 clock source electrical specifications table 14. oscillator and pll specifications (v dd and v ddpll = 3.0 to 3.6 v, v ss = v sspll = 0 v) characteristic symbol min max unit clock source frequency range of extal frequency range ? crystal ? external 1 1 in external clock mode, it is possible to run the chip directly from an extern al clock source without enabling the pll. f crystal f ext 12 0 48.0 50.0 or 60.0 mhz pll reference frequency range f ref_pll 21 0 . 0m h z system frequency 2 ? external clock mode ? on-chip pll frequency 2 all internal registers retain data at 0 hz. f sys 0 f ref / 32 66.67 or 80 3 66.67 or 80 3 3 depending on packaging; see the orderable part number summary. mhz loss of reference frequency 4, 6 4 loss of reference frequency is the reference frequency detected internally, which transitions the pll into self clocked mode. f lor 100 1000 khz self clocked mode frequency 5 5 self clocked mode frequency is the frequency at which t he pll operates when the reference frequency falls below f lor with default mfd/rfd settings. f scm 15m h z crystal start-up time 6, 7 6 this parameter is characterized before qualification rather than 100% tested. 7 proper pc board layout procedures must be followed to achieve specifications. t cst ?0 . 1m s extal input high voltage ? external reference v ihext 2.0 v dd v extal input low voltage ? external reference v ilext v ss 0.8 v pll lock time 4,8 8 this specification applies to the period required for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). t lpll ?5 0 0 s duty cycle of reference 4 t dc 40 60 % f ref frequency un-lock range f ul ?1.5 1.5 % f ref frequency lock range f lck ?0.75 0.75 % f ref clkout period jitter 4, 5, 9 ,10 , measured at f sys max ? peak-to-peak (clock edge to clock edge) ? long term (averaged over 2 ms interval) 9 jitter is the average deviation from the programmed freque ncy measured over the specified interval at maximum f sys . measurements are made with the device powe red by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. 10 based on slow system clock of 40 mhz measured at f sys max. c jitter ? ? 10 .01 % f sys on-chip oscillator frequency f oco 7.84 8.16 mhz because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 32 2.9 usb operation 2.10 mini-flexbus external interface specifications a multi-function external bu s interface called mini-flexbus is provided with basic functionality to inte rface to slave-only devices up to a maximum bus frequency of 80mhz. it can be di rectly connected to asynchronous or synchronous devices such as external boot roms, flash me mories, gate-array logic, or other simple targ et (slave) devices with little or no additional circuitry. for asynchronous devices a simp le chip-select based interface can be used. all processor bus timings are synchronous; that is, input setup/hold and output delay are given in respect to the rising edge o f a reference clock, mb_clk. the mb_clk frequency is half the internal system bus frequency. the following timing numbers indicate when data is latched or dr iven onto the external bus, relative to the mini-flexbus output clock (mb_clk). all other timing relationships can be derived from these values. table 15. usb operation specifications characteristic symbol value unit minimum core speed for usb operation f sys_usb_min 16 mhz table 16. mini-flexbus ac timing specifications num characteristic min max unit notes frequency of operation ? 80 mhz mb1 clock period 12.5 ? ns mb2 output valid ? 8 ns 1 1 specification is valid for all mb_a[19:0], mb_d[7:0], mb_cs [1:0], mb_oe , mb_r/w , and mb_ale. mb3 output hold 2 ? ns 1 mb4 input setup 6 ? ns 2 2 specification is valid for all mb_d[7:0]. mb5 input hold 0 ? ns 2 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 33 figure 5. mini-flexbus read timing figure 6. mini-flexbus write timing 2.11 fast ethernet timing specifications the following timing specs are defined at the chip i/o pin and must be translated appropriatel y to arrive at timing specs/constraints for th e physical interface. mb_clk mb_a[19:x] mb_d[7:0] / mb_r/w mb_ale mb_csn mb_oe mb1 a[19:x] mb2 mb3 mb4 mb5 d[y:0] address mb_a[15:0] mb2 mb3 mb3 mb2 mb_clk mb_a[19:x] mb_d[7:0] / mb_r/w mb_ale mb_csn mb1 a[19:x] data[y:0] mb2 mb3 mb_oe address mb_a[15:0] mb3 mb2 mb3 mb2 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 34 2.11.1 receive signal timing specifications the following timing specs meet the requir ements for mii and 7-wire style interf aces for a range of transceiver devices. figure 7. mii receive signal timing diagram 2.11.2 transmit signal timing specifications figure 8. mii transmit signal timing diagram table 17. receive signal timing num characteristic mii mode unit min max ? rxclk frequency ? 25 mhz e1 rxd[n:0], rxdv, rxer to rxclk setup 1 1 in mii mode, n = 3 5? ns e2 rxclk to rxd[n:0], rxdv, rxer hold 1 5? ns e3 rxclk pulse width high 35% 65% rxclk period e4 rxclk pulse width low 35% 65% rxclk period table 18. transmit signal timing num characteristic mii mode unit min max ? txclk frequency ? 25 mhz e5 txclk to txd[n:0], txen, txer invalid 1 1 in mii mode, n = 3 5? ns e6 txclk to txd[n:0], txen, txer valid 1 ?25 ns e7 txclk pulse width high 35% 65% t txclk e8 txclk pulse width low 35% 65% t txclk valid data rxclk (input) rxd[n:0] rxdv, rxer e3 e4 e1 e2 valid data txclk (input) txd[n:0] txen, txer e7 e8 e5 e6 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 35 2.11.3 asynchronous input signal timing specifications figure 9. mii async inputs timing diagram 2.11.4 mii serial management timing specifications figure 10. mii serial management channel timing diagram 2.12 general purpose i/o timing gpio can be configured for cer tain pins of the qspi, ddr co ntrol, timer, uart, interrupt and usb interfaces. when in gpio mode, the timing specification for these pins is given in table 21 and figure 11 . the gpio timing is met under the following load test conditions: ?50pf/50 for high drive table 19. mii transmit signal timing num characteristic min max unit e9 crs, col minimum pulse width 1.5 ? txclk period table 20. mii serial management channel signal timing num characteristic symbol min max unit e10 mdc cycle time t mdc 400 ? ns e11 mdc pulse width 40 60 % t mdc e12 mdc to mdio output valid ? 375 ns e13 mdc to mdio output invalid 25 ? ns e14 mdio input to mdc setup 10 ? ns e15 mdio input to mdc hold 0 ? ns crs, col e9 mdc (output) e11 mdio (output) mdio (input) e11 e12 e13 valid data e14 e15 valid data e10 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 36 ?25pf/25 for low drive figure 11. gpio timing 2.13 reset timing figure 12. rsti and configuration override timing table 21. gpio timing num characteristic symbol min max unit g1 clkout high to gpio output valid t chpov ?1 0n s g2 clkout high to gpio output invalid t chpoi 1.5 ? ns g3 gpio input valid to clkout high t pvch 9?n s g4 clkout high to gpio input invalid t chpi 1.5 ? ns table 22. reset and configuration override timing (v dd = 3.0 to 3.6 v, v ss = 0 v, t a = t l to t h ) 1 1 all ac timing is shown with respect to 50% v dd levels unless otherwise noted. num characteristic symbol min max unit r1 rsti input valid to clkout high t rvch 9?n s r2 clkout high to rsti input invalid t chri 1.5 ? ns r3 rsti input valid time 2 2 during low power stop, the synchronizers for the rsti input are bypassed and rsti is asserted asynchronously to the system. thus, rsti must be held a minimum of 100 ns. t rivt 5?t cyc r4 clkout high to rsto valid t chrov ?1 0n s g1 clkout gpio outputs g2 g3 g4 gpio inputs 1 r1 r2 clkout rsti rsto r3 r4 r4 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 37 2.14 i 2 c input/output timing specifications table 23 lists specifications for the i 2 c input timing parameters shown in figure 13 . table 24 lists specifications for the i 2 c output timing parameters shown in figure 13 . table 23. i 2 c input timing specifications between i2c_scl and i2c_sda num characteristic min max units 11 start condition hold time 2 t cyc ?ns i2 clock low period 8 t cyc ?ns i3 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 t cyc ?ns i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 t cyc ?ns i9 stop condition setup time 2 t cyc ?ns table 24. i 2 c output timing specifications between i2c_scl and i2c_sda num characteristic min max units 11 1 1 output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in ta b l e 2 4 . the i 2 c interface is designed to scale the actual data transiti on time to move it to the middle of the scl low period. the actual position is affected by the pre scale and division values programmed into the ifdr; however, the numbers given in ta b l e 2 4 are minimum values. start condition hold time 6 t cyc ?n s i2 1 clock low period 10 t cyc ?n s i3 2 2 because scl and sda are open-collector-type outputs, which the processor can only actively drive low, the time scl or sda take to reach a high level depends on external signal capacitance and pull-up resistor values. i2c_scl/i2c_sda rise time (v il = 0.5 v to v ih = 2.4 v) ?? s i4 1 data hold time 7 t cyc ?n s i5 3 3 specified at a nominal 50-pf load. i2c_scl/i2c_sda fall time (v ih = 2.4 v to v il = 0.5 v) ?3n s i6 1 clock high time 10 t cyc ?n s i7 1 data setup time 2 t cyc ?n s i8 1 start condition setup time (for repeated start condition only) 20 t cyc ?n s i9 1 stop condition setup time 10 t cyc ?n s because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 38 figure 13 shows timing for the values in table 23 and table 24 . figure 13. i 2 c input/output timings 2.15 analog-to-digital converter (adc) parameters table 25 lists specifications for th e analog-to-digital converter. table 25. adc parameters 1 name characteristic min typical max unit v refl low reference voltage v ssa ?v ssa + 50 mv v v refh high reference voltage v dda - 50 mv ?v dda v v dda adc analog supply voltage 3.1 3.3 3.6 v v adin input voltages v refl ?v refh v res resolution 12 ? 12 bits inl integral non-linearity (full input signal range) 2 ? 2.5 3lsb 3 inl integral non-linearity (10% to 90% input signal range) 4 ? 2.5 3lsb dnl differential non-linearity ? ?1 < dnl < + 1< + 1lsb monotonicity guaranteed f adic adc internal clock 0.1 ? 5.0 mhz r ad conversion range v refl ?v refh v t adpu adc power-up time 5 ?61 3t aic cycles 6 t rec recovery from auto standby ? 0 1 t aic cycles t adc conversion time ? 6 ? t aic cycles t ads sample time ? 1 ? t aic cycles c adi input capacitance ? see figure 14 ?pf x in input impedance ? see figure 14 ?w i adi input injection current 7 , per pin ? ? 3 ma i vrefh v refh current ? 0 ? ma v offset offset voltage internal reference ? 8 15 mv e gain gain error (transfer path) .99 1 1.01 ? v offset offset voltage external reference ? 39m v i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 39 2.16 equivalent circuit for adc inputs figure 14 shows the adc input circuit during sample and hold. s1 and s2 are always open/closed at the same time that s3 is closed/open. when s1/s2 are closed & s3 is open, one input of the sample and hold circuit moves to (v refh -v refl )/2, while the other charges to the analog input voltage. when the switches are flipped, the charge on c1 and c2 are averaged via s3, with the result that a single-ended analog input is switched to a differential voltage centered about (v refh -v refl )/2. the switches switch on every cycle of the adc clock (open one-half adc clock, closed one-half adc clock). there are additional capacitances associated with the analog input pad, routing, etc., but these do not filter into the s/h output voltage, as s1 pr ovides isolation during the charge-sharing phase. one aspect of this circuit is that there is an on-going input current, which is a fu nction of the analog input voltage, v ref and the adc clock frequency. 1. parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling; 1.8pf 2. parasitic capacitance due to the chip bond pad, esd protection devices and signal routing; 2.04pf 3. equivalent resistance for the channel select mux; 100 s 4. sampling capacitor at the sample and hold circuit. capacitor c1 is normally disconnected from the input and is only connected to it at sampling time; 1.4pf 5. equivalent input impedance, when the input is selected = figure 14. equivalent circuit for a/d loading snr signal-to-noise ratio ? 62 to 66 ? db thd total harmonic distortion ? ? 75 ? db sfdr spurious free dynamic range ? 67 to 70.3 ? db sinad signal-to-noise plus distortion ? 61 to 63.9 ? db enob effective number of bits 9.1 10.6 ? bits 1 all measurements are preliminary pending full characterization, and made at v dd = 3.3v, v refh = 3.3v, and v refl = ground 2 inl measured from v in = v refl to v in = v refh 3 lsb = least significant bit 4 inl measured from v in = 0.1v refh to v in = 0.9v refh 5 includes power-up of adc and v ref 6 adc clock cycles 7 current that can be injected or sourced from an unselected adc signal input without impacting the performance of the adc table 25. adc parameters 1 (continued) name characteristic min typical max unit 1 2 3 analog input 4 s1 s2 s3 c1 c2 s/h c1 = c2 = 1pf (v refh - v refl )/ 2 125w esd resistor 8pf noise damping capacitor 1 (adc clock rate) (1.4 10 -12 ) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 40 2.17 dma timers timing specifications table 26 lists timer module ac timings. 2.18 qspi electrical specifications table 27 lists qspi timings. the values in table 27 correspond to figure 15 . figure 15. qspi timing 2.19 jtag and boundary scan timing table 26. timer module ac timing specifications name characteristic 1 1 all timing references to clkout are given to its rising edge. min max unit t1 dtin0 / dtin1 / dtin2 / dtin3 cycle time 3 t cyc ?ns t2 dtin0 / dtin1 / dtin2 / dtin3 pulse width 1 t cyc ?ns table 27. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 510 t cyc qs2 qspi_clk high to qspi_dout valid ? 10 ns qs3 qspi_clk high to qspi_dout invalid (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 9 ? ns qs5 qspi_din to qspi_clk (input hold) 9 ? ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 41 figure 16. test clock input timing table 28. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. he nce, it is not associated with any timing. symbol min max unit j1 tclk frequency of operation f jcyc dc 1/4 f sys/2 j2 tclk cycle period t jcyc 4 t cyc ?ns j3 tclk clock pulse width t jcw 26 ? ns j4 tclk rise and fall times t jcrf 03ns j5 boundary scan input data setup time to tclk rise t bsdst 4?ns j6 boundary scan input data hold time after tclk rise t bsdht 26 ? ns j7 tclk low to boundary scan output data valid t bsdv 033ns j8 tclk low to boundary scan output high z t bsdz 033ns j9 tms, tdi input data setup time to tclk rise t tapbst 4?ns j10 tms, tdi input data hold time after tclk rise t tapbht 10 ? ns j11 tclk low to tdo data valid t tdodv 026ns j12 tclk low to tdo high z t tdodz 08ns j13 trst assert time t trstat 100 ? ns j14 trst setup time (negation) to tclk high t trstst 10 ? ns tclk v il v ih j3 j3 j4 j4 j2 (input) because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 electrical characteristics freescale semiconductor 42 figure 17. boundary scan (jtag) timing figure 18. test access port timing figure 19. trst timing input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih j5 j6 j7 j8 j7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih j9 j10 j11 j12 j11 tclk trst 14 13 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
electrical characteristics mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 43 2.20 debug ac timing specifications table 29 lists specifications for the debug ac timing parameters shown in figure 21 . figure 20 shows real-time trace ti ming for the values in table 29 . figure 20. real-time trace ac timing table 29. debug ac timing specification num characteristic 66/80 mhz units min max d1 pst, ddata to clkout setup 4 ? ns d2 clkout to pst, ddata hold 1.5 ? ns d3 dsi-to-dsclk setup 1 t cyc ?ns d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. dsclk-to-dso hold 4 t cyc ?ns d5 dsclk cycle time 5 t cyc ?ns d6 bkpt input data setup time to clkout rise 4 ? ns d7 bkpt input data hold time to clkout rise 1.5 ? ns d8 clkout high to bkpt high z 0.0 10.0 ns clkout pst[3:0] d2 d1 ddata[3:0] because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
mcf52259 coldfire microcontroller, rev. 3 package information freescale semiconductor 44 figure 21 shows bdm serial port ac timing for the values in table 29 . figure 21. bdm serial port ac timing 3 package information the latest package outline drawings are available on the product summary pages on http://www.freescale.com/coldfire . table 30 lists the case outline numbers per device. use these numbers in the web page?s keyword search engine to find the latest package outline drawings. table 30. package information device package type case outline numbers mcf52252 100 lqfp 98ass23308w mcf52254 mcf52255 mcf52256 144 lqfp or 144 mapbga 98ass23177w 98ash70694a mcf52258 mcf52259 dsi dso current next clkout past current dsclk d3 d4 d5 because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
revision history mcf52259 coldfire microcontroller, rev. 3 freescale semiconductor 45 4 revision history table 31. revision history revision description 0 initial public release. 1 ? added package dimensions to package diagrams ? added listing of devices for mcf52259 family ? changed ?four-channel general-purpose timer (gpt) capable of input capture/output compare, pulse width modulation (pwm), and pulse accumulation? to ?four-channel general-purpose timer (gpt) capable of input capture/output compare, puls e width modulation (pwm), pulse-code modulation (pcm), and pulse accumulation? ? updated the figure pinout top view (144 mapbga) ? removed an extraneous instance of the table pin functions by primary and alternate purpose ? in the table pin functions by primar y and alternate purpose , changed a footnote from ?this list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the adc? to ?this list for power and ground does not include those dedicated power/ground pins included elsewhere, such as in the adc, usb, and pll? ? in the table sgfm flash program and erase characteristics , changed ?(v ddf = 2.7 to 3.6 v)? to ?(v dd = 3.0 to 3.6 v)? ? in the table sgfm flash module life characteristics , changed ?(v ddf = 2.7 to 3.6 v)? to ?(v dd = 3.0 to 3.6 v)? ? in the table oscillator and pll specifications , changed ?v dd and v ddpll = 2.7 to 3.6 v? to ?v dd and v ddpll = 3.0 to 3.6 v? ? in the table reset and configuration override timing , changed ?v dd = 2.7 to 3.6 v? to ?v dd = 3.0 to 3.6 v? 2 ? added ezport electrical specifications. ? updated ta b l e 2 for part numbers. ?in ta b l e 3 , added slew rate column, updated derive strength, pull-up/pull-down values,jtag pin alternate functions, removed wired/or control colu mn, and reordered an[7:0] list of pin numbers for 144 lqfp and 100 lqfp. ? updated ta b l e 1 4 . ? updated ta b l e 1 3 , to change min voltage spec for standb y voltage (vstby) to 1.8v (from 3.0v). ? updated figure 2 for rtc_extal and rtc_xtal pin positions. 3 ? updated ezport electrical specifications ? added hysteresis note in the dc electrical table. ? clarified pin functi on table for vss pins. ? clarified orderable part summary. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages
document number: mcf52259 rev. 3 5/2010 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2010. all rights reserved. because of an order from the united states international trade commission, bga-packaged product lines and part numbers indicated here currently are not available from freescale for import or sale in the united states prior to september 2010: mcf52256, mcf52258, and mcf52259 products in 144 mapbga packages

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